1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the 1st PLL is 16.8 MHz and the output is 268.8 MHz for CLKOP. To get these settings the divider ratio is 16/1.

In the test-bench, the input frequency for a PLL is typically defined using a clock period which is specified down to the nearest ps; i.e. 59.524 ns for our 16.8 MHz example. When this value is multiplied by the divider values ratio the result is a repeating decimal which the simulator cannot resolve exactly; in our example 3.72025 ns.

The simulator will resolve this to 2 different clock periods, one which is 3.720 ns and the other is 3.722 ns. It will use the 3.720 ns for most of the clock cycles but will occasionally substitute the 3.722 ns value to keep the clock rising edge in the correct location over a large number of cycles. The CLKOP from the 1st PLL is the input to the 2nd PLL so this change in the clock period will be seen as jitter by the 2nd PLL. Unfortunately, the PLL simulation model does not handle this jitter so the 2nd PLL loses lock and the PLL outputs will go low.

The solution is to use a clock period in the simulation which will avoid a repeating decimal value for the output clock period after being multiplied by the divider values ratio.

Use a value of 59.2 ns for the clock period in the simulation test-bench rather than 59.524 ns for our example and the simulation will work correctly. This corresponds to an input frequency of 16.892 MHz and an output of 270.27 MHz (clock period = 3.7 ns) for the 1st PLL.

These frequencies are close enough to what the customer is using to prove the their design is working correctly. Remember that this is only a simulation issue. The actual PLL will accept a certain amount of jitter on its input as shown in the data sheet and will not be affected by this issue. The actual PLL will operate at the frequencies chosen within the tolerances shown in the data sheet.

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1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

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793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?

2469 - LatticeECP3: Why does the PLL simulation model act differently than hardware?

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6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.