6430 - CertusPro-NX / ADC: Why is a PLL used to drive the ADC adc_clk_i pin and not directly driven by an oscillator output?
Description:This article explains the reason ADC clock-in cannot be driven using an oscillator output in CertusPro-NX.
Solution:In CertusPro-NX., the ADC clock input is hard-wired on the fabric to the 4th secondary output (CLKOS4) of the Lower Right Corner (LRC) PLL in the silicon. This connection is not re-routable, thus ADC clock input has to be driven using PLL.
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