1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?  

It is common for most of today’s FPGA’s to provide multiple PLLs to support the flexible clock requirements needed for today's complex system design. The PLL has a specific frequency operational range. For example, the LatticeXP2 datasheet indicates the PLL, reference input clock must be between 10 - 435 Mhz. (for more details specification refer to datasheet DS1009).

For other FPGA device families, refer to Lattice website for datasheet details (http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_category&document_type=32&source=topnav).

The reason for these specifications is that each PLL for each FPGA family is designed to have an optimal setting for maximum flexibility under various operation conditions. If input frequency of the reference clock that feeds the PLL, is too slow or too fast thus outside of the spec range defined in the datasheet, it can cause the PLL to fail to obtain lock or maintain lock once obtained. Additionally, it also will increase the jitter level of the PLL output.

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1686 - What&nbsp;is&nbsp;the impact and potential problems&nbsp;when&nbsp;the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet? &nbsp;

1686 - What&nbsp;is&nbsp;the impact and potential problems&nbsp;when&nbsp;the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet? &nbsp;

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6287 - ICE40 UltraPlus: Does any GBIN input pin can be used to drive the reference clock input to the PLL?

1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?

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6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?

1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?