5253 - iCE40 UltraPlus: Is the Reset signal in PLL generation synchronous or asynchronous in Lattice iCE40?

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• 6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

  Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...

• 6131 - Certus-Nx: Are the outputs of the Nexus platform's sysCLOCK PLL synchronous signals?

  Solution: Yes, the outputs of the PLL (e.g. CLKOP, CLKOS, CLKOS2, etc.) are synchronous signals. But you can introduce dissimilar phase shifts to the outputs, either through static or dynamic mode phase adjustment which is available on the Nexus ...

• 7738 - Can Global Set/Reset resources be analyzed in Radiant STA tools with Avant?

  Global Set/Reset resources cannot be analyzed in STA tools for both Nexus and Avant devices. For the resource's useability, Users may refer to Global Set/Reset Usage for Nexus Platform Application note found in ...

• 793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?

  Definition: The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL. For some applications users may use this LOCK signal as a flag or control signal ...

• [MachXO2/MachXO3] Upon power‑up, how can we estimate the time between POR and PLL lock?

  To estimate the time between POR and PLL lock, add the tREFRESH duration to the tLOCK duration.