4777 - iCEcube2: Placer error saying the PLL instance cannot be placed.

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• 4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."

  For Phase and Delay compensation modes of PLL, the PLL configuration tool of iCECube shows the following error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz.". However, the data sheet indicates that the max ...

• 3899 - iCECube2 / iCE40 / PLL: What is the difference between selecting "PACKAGEPIN" and "General Purpose IO Pad or Core Logic" options during PLL generation?

  Solution: If the "Dedicated Clock Pad (single ended)" is selected during the PLL generation, the IO pin connected to the PLL's "PACKAGEPIN" becomes dedicated and hence, the signal coming in from that IO pin can't be used for any other logic design in ...

• 5898 - iCE40 UltraPlus: With an iCE40 Ultraplus device, how to drive an external pin with a PLL output using Radiant Software?

  There are 2 types of PLL outputs that you can use. In Radiant Software, these port outputs are named as "outcore" and "outglobal". After generating the PLL using the IP catalog, you will still need a Top-level module to instantiate the generated PLL. ...

• 3678 - <span id="lf104285">PLL: When does the lock of PLL lose?</span>

  Description: There could be several reasons for Phase Lock Loop (PLL) losing the lock. 1.If the input clock or feedback signals to the PLL become invalid. 2.If there is Noise in the PLL power supply. 3.If the input clock Period Jitter (tIPJIT) of the ...

• 1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

  My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the ...