3682 - LatticeECP2/M: What should be the LOCK_SENSITIVITY bit in DQSDLL for DDR interface?
Description:
The setting of LOCK_SENSITIVITY bit depends on the operating frequency of DLL:
- If the DLL is operated at or above 150 MHz (more sensitive to jitter), set LOCK_SENSITIVITY bit HIGH.
For higher frequencies, the system should
be more robust, so the lock detect circuit is programmed to be more sensitive
to jitter. It loses lock if the system has jitter.
- If the DLL is operated at or below
100 MHz (less sensitive to jitter), set LOCK_SENSITIVITY bit LOW.
For lower frequencies, the jitter may not affect
the valid window, so lock detect circuit can be programmed to be more tolerant
to jitter.
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