2530 - Generic DDR Simulation: glitches in functional simulation, but not in timing simulations for an output DDR (Double Data Rate) interface
Description:
In the GDDRX2_TX Aligned interface, the ECLKSYNC, CLKDIV, DQSBUFE1 and SCLK routing delay timing will generate the required phase relationship between SCLK and DQCLK1 inside the ODDRX2D module so data will be correctly transferred between the 2 clocks.
Solution:
It is required that SCLK be delayed from the DQCLK1 edge for the data to be captured without any glitches. There is enough delay generated by the CLKDIV and primary clock routing on SCLK for it to occur after the DQCLK1 edge generated by DQSBUFE1. These delay values do not show up in the functional simulation since function simulation does not include the hardware delay numbers. Hence, there are glitches in functional simulation that do not appear in timing simulation.
As a workaround for functional simulation, add a 1ns delay in the HDL on the SCLK path to emulate the hardware delay. By doing this, the glitches on the output data should disappear.
This will also apply to the GDDRX2_TX.PLL.Centered and GDDRX2_TX.DQSDLL.Centered interfaces. Please refer to (ECP3 High Speed IO Interface Technote TN1180) for detailed description of this timing requirement.