2519 - LatticeECP3 : Why does LatticeECP3 Generic DDR (Double Data Rate) design generates missing attribute errors?

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• 7096 - DDR: Can the "DDR_Generic" Module in Lattice Radiant and Diamond software which has DDR communication supports bidirectional input and output?

  The Generic Double Data Rate Input/Output (GDDR I/O) Module has separate receive DDR interface and transmit DDR interface, it doesn't support the use of GDDRx1 pin as input and the same pin as output. The 'Interface Type' option in IP Catalog for DDR ...

• 2530 - Generic DDR Simulation: glitches in functional simulation, but not in timing simulations for an output DDR (Double Data Rate) interface

  Description: In the GDDRX2_TX Aligned interface, the ECLKSYNC, CLKDIV, DQSBUFE1 and SCLK routing delay timing will generate the required phase relationship between SCLK and DQCLK1 inside the ODDRX2D module so data will be correctly transferred ...

• 2637 - ECP3: Can on-chip parallel termination to <!--[if gte mso 9]><xml> <o:OfficeDocumentSettings> <o:AllowPNG/> </o:OfficeDocumentSettings> </xml><![endif]-->V_TTbe used when implementing Generic DDR interface on LatticeECP3 device?

  Description: An on-chip parallel termination to VTT can be used when implementing Generic DDR interface on LatticeECP3 device. However, the same is not possible for DDR interfaces. External termination to VTT is required for DDR interfaces. All DQ ...

• 1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

  My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the ...

• 3024 - <span id="lf104285">What are the various ways to produce RAM/ROM in a design? What is the power up state or content of an inferred RAM?</span>

  There are two ways to produce RAM and ROM in a design. You can write code for the design so that the synthesis tool infers the memory or you can instantiate predefined IPexpress or PMI (Parametrized Module Instantiation) memory modules.Inferring ...