7096 - DDR: Can the "DDR_Generic" Module in Lattice Radiant and Diamond software which has DDR communication supports bidirectional input and output?

• Related Articles

• 5898 - iCE40 UltraPlus: With an iCE40 Ultraplus device, how to drive an external pin with a PLL output using Radiant Software?

  There are 2 types of PLL outputs that you can use. In Radiant Software, these port outputs are named as "outcore" and "outglobal". After generating the PLL using the IP catalog, you will still need a Top-level module to instantiate the generated PLL. ...

• 2530 - Generic DDR Simulation: glitches in functional simulation, but not in timing simulations for an output DDR (Double Data Rate) interface

  Description: In the GDDRX2_TX Aligned interface, the ECLKSYNC, CLKDIV, DQSBUFE1 and SCLK routing delay timing will generate the required phase relationship between SCLK and DQCLK1 inside the ODDRX2D module so data will be correctly transferred ...

• 2519 - LatticeECP3 : Why does LatticeECP3 Generic DDR (Double Data Rate) design generates missing attribute errors?

  IDDRAPPS and ODDRAPPS attributes are required for all DDR interfaces to indicate the type of interface being generated by the software. When the DDR interface is generated through IPexpress it will generate HDL that includes the correct values for ...

• 5568 - Diamond/MachXO3: How to use the Lattice primitives in this device family?

  DescriptionL Please check the FPGA Libraries Reference Guide. Open Diamond Software -> Start Page -> Look for the "Reference Guides" -> Diamond [DIAMOND VERSION] FPGA Libraries (PDF version) Actual Libraries can be found in the following directories ...

• 235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?

  Description: The IPexpress tool within Lattice development software allows user to generate FIFO_DC using Embedded Block Ram (EBR) or distributed memory. During the generation of the FIFO_DC module, there are options to use output registers, and/or ...