6213 - All Nexus Devices : Why PLL IP is not able to meet the BW_FACTOR requirement for more complex cases than dividing or multiplying by 2? For example, reference clock 45MHZ, the output is 11.25 MHz (/4).

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• 4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."

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• 1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?  

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• 6441 - PLL for Nexus FPGAs: How to dynamically change the PLL output frequency?

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