DDR3 / DDR3L
2427 - LatticeECP3: Unable to assign the DDR3 memory clock (CK) pads to Bank 1 during the
DDR3 core generation when running DDR3 interface running at 300MHz. How to use the pins
in Bank 1 for CK?
LatticeECP3 has the following pinout guideline for a DDR3 CK pair assignment: It's recommended that the CK pads are located on the same side as data pads when the DDR3 bus is running at high speed (400MHz). At a lower operating speed such as 333 or ...
5439 - LatticeECP5: How is the detection algorithm of the Read Training error (IP port name: rt_err) and when is it asserted?
Description: Read Training error indicates failure in Read Training process. The PHY IP will not work properly if there is a Read Training error. This signal should be checked when init_done signal is asserted.
2324 - [LatticeECP3]: Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?
If the user is using a Lattice DDR3 memory controller IP core version 1.2 or later, the user can use a different rate of input reference clock. The original clock synchronization module (CSM) in the earlier version DDR3 IP cores require the fixed ...
2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?
The "read_pulse_tap" port is an input signal to the DDR3 controller IP core. Each DQS group has its own 3-bit read_pulse_tap port to control the READ signal timing to the DQSBUF hardware module. The DDR3 IP core allows dynamic READ pulse timing ...
1792 - [LatticeECP3]: Can I connect both the "mem_rst_n" and "rst_n" signals in the Lattice
DDR3 IP core together to a system reset to meet the JEDEC initialization
requirement?
The "rsn_n" signal resets both the DDR3 memory controller and the DDR3 memory devices while the "mem_rst_n" signal resets only the DDR3 memory devices. The JEDEC specification has two different cases of reset initialization. Power-up reset ...
2294 - DDR3 PHY: What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?
Both the data and address/command bus loading factors should be considered to answer the question. The Lattice DDR3 controller and DDR3 PHY IP cores were validated to allow up to two-DDR3 data pin loading on the DQ, DQS and DM signals at the rate of ...
2246 - LatticeECP3: I migrated my design from DDR2 to DDR3 and noticed that there are two
more edges on DQS during the write operation. Why does the DDR3
controller IP core behave like this?
Description: This is because of the difference of write preamble between the DDR2 and DDR3 interfaces. JEDEC (Joint Electron Devices Engineering Council) DDR2 specification requires the write preamble to keep DQS "low" for longer than 0.35 tCK from ...
2244 - LatticeECP3: I need to use four chip select signals while the Lattice DDR3 controller
IP core supports only up to two. Can I extend the number of chip select
from the core?
Description: No. Lattice DDR3 controller IP core does not support more than 2 chip selects. The IP core was designed and validated to support upto two ranks of DDR3 memory configurations. Since each rank is controlled by a corresponding chip select ...
2218 - LatticeECP3/DDR3 SDRAM Controller v1.3.0 and up: For DDR3 controller IP core v1.3, why does the
simulation result fail while the design works well without a failure on
the board?
The READ_PULSE_TAP handling guideline has been changed for the DDR3 memory controller IP v1.3 core (or later version). READ_PULSE_TAP is a user controlled input to the core to compensate for the DQS round trip delay in a DDR3 memory controller IP ...
5261 - ECP5/ECP5-5G: Does DDR3 SDRAM controller IP support DDR3L?
Yes, the DDR3 SDRAM controller IP support DDR3L 1.5V operation. It also supports 1.35V operation, but SSTL15 should be changed to SSTL135. Refer to the ECP5 and ECP5-5G sysIO Usage Guide (FPGA-TN-02032).
2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?
In DDR memory interfaces, the CK rising edge is located ideally right in the middle of the address and command eyes to maximize the tIS and tIH margin. LatticeECP3 allows this by generating the CK and the address/command signals from the same phase ...
1736 - LatticeECP3: What is your recommendation to reduce or eliminate SSO noise related issues for DDR3 interface implementation using a LatticeECP3 device?
The following are the general SSO (simultaneous switching output) considerations and guidelines for DDR3 interface implementations: Proper termination is needed to minimize SSO impacts. With sub-optimal termination, the SSO noise can be aggravated ...
2174 - LatticeECP3/DDR3 SDRAM Controller: How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?
Integrating multiple DDR3 interfaces into a LatticeECP3 device can be done using one of the following cases depending on the locations of the DDR3 interfaces. 1. When locating all DDR3 interfaces on one side (either the left or right side): Sharing ...
1697 - DDR3/DDR3L: Why do I have an error during the mapping of a DDR3 IP-based design, saying "Error: Output buffer drives output buffer: each IO pad requires one and only one buffer..."?
This map error is caused by the duplicated IO buffers which are located both inside the IP core netlist file (.ngo) and your top-level code that instantiates the IP core netlist. DDR3 IP cores already include all the IO buffers for the DDR3 bus ...
1675 - LatticeECP3: Why does ispLEVER & Lattice Diamond Place and Route generate errors
when I assign DDR3 Address or Command output signals to DQS pins?
For DDR3, the Address & Command outputs are generated using the DDR registers(ODDRXD1 modules). The DQSP and DQSN pins do not support DDR registers hence the error. These outputs will need to be assigned to non-DQS pins. Please see section "DDR3 ...
2102 - LatticeECP3 : Does it support the 1.35V operation mode of the 1.35V DDR3 SDRAM?
The DDR3L 1.35V devices support both the 1.5V and 1.35V operation modes. LatticeECP3 can support the DDR3L 1.35V devices when both are running in the 1.5V operation mode. This is because LatticeECP3 devices do not have 1.35V IO support. If you run a ...
2684 - DDR3 IP: Why do I have two top-level wrappers inside a DDR3 IP core package generated from IPexpress ? Which one should I use for my design?
The DDR3 IP core package includes two top-level wrapper files in two different places using the same name, ddr3_sdram_mem_top_wrapper.v or .vhd. One of them which is located in the directory "ddr_p_eval\<user_name>\impl" is used solely for the core ...
1651 - LatticeECP3: Can the CLKP/CLKN outputs of the DDR3 memory controller be placed on the top side of the LatticeECP3 device?
The DDR3 (Double Data Rate - 3) CLKP/CLKN pads use a generic output DDR function (ODDR). The recommendation is to place the CLKP/CLKN outputs on the same side that the DQ and DQS pads are located. This is because the top side pads are not for the ...
2087 - LatticeECP3/DDR3: How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of multiple of 4x (1:4:2)?
The CSM (Clock Synchronization Module) module of the DDR3 memory controller ipcore multiplies the input reference clock frequency four times for the DDR3 bus operations and two times for the local bus operations. This means that the DDR3 IP core uses ...
2041 - LatticeECP3: How to place DDR3 interface pins to minimize the SSO impact?
1. Try to use the DQS groups in the middle of the (right or left) edge if the DDR3 data width does not require to use the whole edge of LatticeECP3. Avoid the corner DQS groups if possible. 2. Locate a spacer DQS group between two adjacent data DQS ...
2583 - DDR3 IP: Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?
During initialization The DDR3 controller IP core performs both ZQ calibration long (ZQCL) and auto refresh commands during the DDR3 initialization process. It is a requirement defined by JEDEC DDR3 specification. After initialization After the ...
297 - DDR/DDR2/DDR3: How do I implement differential SSTL pads in software for my DDR memory interface design?
Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called "IOBUF". You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, ...
2527 - LatticeECP3: Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors. How can this happen?
Description: There are two possibilities: 1. The signal paths in the ignored preferences may not be correct. This usually happens when a user takes the IP core preferences as-is without getting them localized. If there is any added hierarchy, the ...
5627 - DDR3 3.1 IP Core : Why is the DDR3 IP core is not accessible for ECP3 device when using LSE?
Currently, when the device selected is ECP3, DDR3 IP package supports Synplify only. It does not support LSE. When the device selected is ECP5, DDR3 IP package supports both Synplify and LSE.
2474 - LatticeECP3: Does the DDR2/3 SDRAM Controller IP evaluation design and testbench from IPexpress support SDF timing simulations?
The DDR2/3 SDRAM Controller IP evaluation reference design from IPexpress maps the IP Core user side IOs to buffers. As a result, the routing delay from the last flip flop to the IO is large. Since the simulation testbench drives and monitors these ...