1675 - LatticeECP3: Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?  

For DDR3, the Address & Command outputs are generated using the DDR registers(ODDRXD1 modules). The DQSP and DQSN pins do not support DDR registers hence the error. These outputs will need to be assigned to non-DQS pins.

Please see section "DDR3 Pinout Guidelines" in Technical Note TN1180 for all the DDR3 pinout rules.

Related Articles
1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?
DDR (Double Data Rate) memory interfaces use SSTL signaling which requires parallel termination to VTT at the receiver side. The external VTT termination on data is for the memory controller side during the read operations. Since the address, command ...
297 - DDR/DDR2/DDR3:  How do I implement differential SSTL pads in software for my DDR memory interface design?
Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called "IOBUF". You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, ...
2041 - LatticeECP3: How to place DDR3 interface pins to minimize the SSO impact?
1. Try to use the DQS groups in the middle of the (right or left) edge if the DDR3 data width does not require to use the whole edge of LatticeECP3. Avoid the corner DQS groups if possible. 2. Locate a spacer DQS group between two adjacent data DQS ...
833 - Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?
Lattice Diamond: ECP2M: PCS: Yes, you can control where an LatticeECP2M (Physical Coding Sublayer) PCS block is located. The PCS blocks on an LatticeECP2M device can be located at either the upper right, upper left, lower right or lower left. These ...
2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?
In DDR memory interfaces, the CK rising edge is located ideally right in the middle of the address and command eyes to maximize the tIS and tIH margin. LatticeECP3 allows this by generating the CK and the address/command signals from the same phase ...

1675 - LatticeECP3: Why does&nbsp;ispLEVER &amp; Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins? &nbsp;

1675 - LatticeECP3: Why does&nbsp;ispLEVER &amp; Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins? &nbsp;

Related Articles

1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?

297 - DDR/DDR2/DDR3:&nbsp; How do I implement differential SSTL pads in software for my DDR memory interface design?

2041 - LatticeECP3: How to place DDR3 interface pins to minimize the SSO impact?

833 - Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?

2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?

1675 - LatticeECP3: Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?

1675 - LatticeECP3: Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?

297 - DDR/DDR2/DDR3: How do I implement differential SSTL pads in software for my DDR memory interface design?