1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?

DDR (Double Data Rate) memory interfaces use SSTL signaling which requires parallel termination to VTT at the receiver side. The external VTT termination on data is for the memory controller side during the read operations. Since the address, command and control signals are output from the memory controller, VTT termination is not required at the controller side. Therefore, the address, command and control signals need to be terminated to VTT at the memory side because the DDR2/3 memory is the receiver for these signals.

It is required that the external termination resistors on the data signals are located as close to the ECP3 pins as possible with not longer than 600-mil (0.6") trace length. We recommend you run signal integrity (SI) Simulation to determine the best termination value. If SI simulation is not available, parallel termination of 100~120 ohms to VTT for DDR3 (75 ohms for DDR2) is recommended.

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1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?

1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?

Related Articles

2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?

1675 - LatticeECP3: Why does&nbsp;ispLEVER &amp; Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins? &nbsp;

356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

833 - Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?

1076 - LatticeECP2/XP2: How many DDR memory interfaces can be implemented on a single FPGA device?

1675 - LatticeECP3: Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?