2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?

In DDR memory interfaces, the CK rising edge is located ideally right in the middle of the address and command eyes to maximize the tIS and tIH margin. LatticeECP3 allows this by generating the CK and the address/command signals from the same phase clocks (2x and 1x, respectively) then inverting the CK output phase. Since the CK and address/command generations use the dedicated DDR IO blocks, there is no outstanding data-path skew difference between them. However, there is a clock skew difference between them and the difference is clearly listed in the datasheet. Since both CK and the address/command signals are driven by the primary clocks from the same PLL, take the maximum primary clock net skew data to determine the worst case window from the datasheet.

See the "LatticeECP3 External Switching Characteristics" table in the LatticeECP3 datasheet. Find your device and apply the number for the following cases:

1. tSKEW_PRIB: take this if DDR3 address/commands and CK are inside the same bank
2. tSKEW_PRI: take this if DDR3 address/commands and CK are located in different banks

Note that the numbers in the table include both the clock distribution skew and IO pad skew.

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2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?

2191 - [LatticeECP3] Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?

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2427 - LatticeECP3: Unable to assign the DDR3 memory clock (CK) pads&nbsp;to Bank 1 during the DDR3 core generation when running DDR3 interface running at&nbsp;300MHz. How to use the pins in Bank 1 for CK?

1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?

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1675 - LatticeECP3: Why does&nbsp;ispLEVER &amp; Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins? &nbsp;

2427 - LatticeECP3: Unable to assign the DDR3 memory clock (CK) pads to Bank 1 during the DDR3 core generation when running DDR3 interface running at 300MHz. How to use the pins in Bank 1 for CK?

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