297 - DDR/DDR2/DDR3: How do I implement differential SSTL pads in software for my DDR memory interface design?
Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called "IOBUF". You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, in your RTL, like any other single ended I/O. The software automatically assigns the negative-end pads by using IO_TYPE=SSTL18D_II (SSTL25D_II for DDR1, SSTL15D for DDR3) attribute in combination with the IOBUF preference to implement differential SSTL type. See the following example:
In RTL:
(Verilog)
output em_ddr_clk;
inout em_ddr_dqs;
(VHDL)
em_ddr_clk out std_logic;
em_ddr_dqs inout std_logic;
In the preference file (.lpf):
LOCATE COMP "em_ddr_clk" SITE "U2";
IOBUF PORT "em_ddr_clk" IO_TYPE=SSTL18D_II;
LOCATE COMP "em_ddr_dqs" SITE "AM6";
IOBUF PORT "em_ddr_dqs" IO_TYPE=SSTL18D_II;
After the design has the logic mapped and placed, the pad report file (.pad) will show the positive and negative pin assignment:
| U2/6 | em_ddr_clk+ | SSTL18D_II_OUT | PL62A | LDQ67 |
| U1/6 | em_ddr_clk- | SSTL18D_II_OUT | PL62B | LDQ67 |
| AM6/6 | em_ddr_dqs+ | SSTL18D_II_BIDI | PL121A | LDQS121 |
| AN6/6 | em_ddr_dqs- | SSTL18D_II_BIDI | PL121B | LDQ121 |