It's recommended that the CK pads are located on the same side as data pads when the DDR3 bus is running at high speed (400MHz).
At a lower operating speed such as 333 or 300MHz, however, CK can be located on either the same side as data pads or a top-side bank. In this example, both Bank 0 and Bank 1 are legal locations to accommodate a CK pair if your target speed is 300MHz or 333MHz. The reason why the DDR3 IP core allows only Bank 0 in this case is because assigning the CK pad to Bank 1 is generally not practical in terms of pin resource allocation and static timing achievement. If the CK pads are located on the other side of the top bank, for example, it may cause a static timing failure if the internal routing delays are excessive. Although a pair in Bank 1 can be used as CK, the DDR3 IP core does not encourage you to use it due to this reason.
Need to use a pair in Bank 1, you can generate a DDR3 IP core with CK assigned to Bank 0 first. Then, the user can simply update the target bank for the CK pair from Bank 0 to Bank 1 in the preference file (.LPF) as shown below.
DEFINE PORT GROUP "EM_DDR_CLK_GRP" "em_ddr_clk_*" ;
IOBUF GROUP "EM_DDR_CLK_GRP" IO_TYPE=SSTL15D BANK=1 ;
The user will need to make sure not to violate the static timing requirement.