The following are the general SSO (simultaneous switching output) considerations and guidelines for DDR3 interface implementations:

1. Proper termination is needed to minimize SSO impacts. With sub-optimal termination, the SSO noise can be aggravated because the signal energy has no place to go but into the supply or ground plane. Follow the DDR3 termination guideline specified in TN1180.
2. Write leveling is the best way to decrease SSO. Make sure you turn on the Write Leveling option during the core generation if your application uses DDR3 DIMM. Write leveling will spread the read DQS/DQ arrival time to FPGA in time domain, which essentially spreads out noise and makes its peak noise level much lower.
3. Check your slew rate and drive strength settings. When you use slow slew and 8mA SSTL15 driving strength is 8mA, it would generate less amount of SSO compared to fast slew and 10mA.
4. Check the noise on VCCIO when the SSO noise is measured. If you see the same or similar pattern of noise on VCCIO, this could be a contributor to the noise. If you see the same noise, the pseudo powering will be helpful. Use of pseudo power pads helps noticeably decrease SSO. This would be an effective way to tame SSO noise. If you have unused I/O pads in the DDR3 banks, make them to be pseudo VCCIO and GND pads by connecting them to the VCCIO power and GND source on the PCB. Then set them to OUTPUT with driving High with maximum driving strength. You can set SSTL15 10mA output for them. They will provide more VCCIO power and stable grounding and decrease SSO noise. It is recommended more than 2/3 of pseudo power pads be connected to VCCIO.
5. Spread data DQS group pads as much as possible in a bank. If you have 7 DQS groups in a bank and want to implement a 32-bit DDR3, for example, having them assigned to "d,x,d,x,d,x,d" will have significantly lower SSO impact than a consecutive pad assignment like "x,x,d,d,d,d,x". (where x: non-data DQS, d: data DQS)
6. If SSO noise on the address and control signals is concerned, use of series termination resistors on the address/command lines would help decrease SSO. 22-ohm or smaller value is recommended.
7. Isolating the address and command signals from the switching DQ signals to a different bank is also a good way to decrease SSO.
8. Probe measurement is also an important factor due to added noise from the ground loops and plane resonances. Make sure the ground lead of the probe is as short as possible, preferably less than 1/2 inch.
9. Well considered PCB layout is crucial to minimize the system's SSO impact. Follow the generally known high-speed PCB implementation guidelines.