2218 - LatticeECP3/DDR3 SDRAM Controller v1.3.0 and up: For DDR3 controller IP core v1.3, why does the
simulation result fail while the design works well without a failure on
the board?
The READ_PULSE_TAP handling guideline has been changed for the DDR3
memory controller IP v1.3 core (or later version). READ_PULSE_TAP is a
user controlled input to the core to compensate for the DQS round trip
delay in a DDR3 memory controller IP based interface. The previous
versions include the DQS round trip delay inside the simulation model
with a fixed value "2" (3b'010 for each DQS group). Since the DQS round
trip delay is a user variable, a decision was made to remove the fixed
round trip delay from the core simulation model. This requires modelling the actual round trip delay in your test bench environment or use
the zero READ_PULSE_TAP value when no round trip delay is modeled in
your functional simulation environment.
If no round trip delay modeling is used in your test bench, The READ_PULSE_TAP value for each DQS group needs to be zero (3'b000) for the simulation no matter what a READ_PULSE_TAP value is used for the actual hardware implementation.
When generating a UDIMM based DDR3 core, for example, the recommended initial READ_PULSE_TAP value is "2" (3'b010) for each DQS group. For your functional simulation, use "0" (3'b000) if not modelling the actual HW round trip delay of your system in your test bench.