2246 - LatticeECP3: I migrated my design from DDR2 to DDR3 and noticed that there are two more edges on DQS during the write operation. Why does the DDR3 controller IP core behave like this?

2246 - LatticeECP3: I migrated my design from DDR2 to DDR3 and noticed that there are two more edges on DQS during the write operation. Why does the DDR3 controller IP core behave like this?

Description:
This is because of the difference of write preamble between the DDR2 and DDR3 interfaces. JEDEC (Joint Electron Devices Engineering Council) DDR2 specification requires the write preamble to keep DQS "low" for longer than 0.35 tCK from the high-impedance until the first rising edge of DQS centered with the first write data. In DDR3, however, JEDEC defined the DDR3 write preamble (tWPRE) to be minimum 0.9 tCK including the first rising and falling edge of DQS from the high-impedance state. Due to this difference, what you observed is a JEDEC compliant behavior. For a DDR3 memory controller to perform a new write operation, these preamble edges must be present to communicate with any existing JEDEC compliant DDR3 memory device.