2102 - LatticeECP3 : Does it support the 1.35V operation mode of the 1.35V DDR3 SDRAM?

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• 5261 - ECP5/ECP5-5G: Does DDR3 SDRAM controller IP support DDR3L?

  Yes, the DDR3 SDRAM controller IP support DDR3L 1.5V operation. It also supports 1.35V operation, but SSTL15 should be changed to SSTL135. Refer to the ECP5 and ECP5-5G sysIO Usage Guide (FPGA-TN-02032).

• 7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

  Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...

• 2474 - LatticeECP3: Does the DDR2/3 SDRAM Controller IP evaluation design and testbench from IPexpress support SDF timing simulations?

  The DDR2/3 SDRAM Controller IP evaluation reference design from IPexpress maps the IP Core user side IOs to buffers. As a result, the routing delay from the last flip flop to the IO is large. Since the simulation testbench drives and monitors these ...

• 297 - DDR/DDR2/DDR3:  How do I implement differential SSTL pads in software for my DDR memory interface design?

  Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called "IOBUF". You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, ...

• 1691 - LatticeECP3: Can LatticeECP3 support OC3/OC12/OC48 SONET/SDH framer or mapper applications?  

  LatticeECP3 has SERDES block that can run in simple 8-bit-only mode to support SDH/SONET (Synchronous Digital Hierarchy/ Synchronous Optical Networking) framer and mapper applications. System requirement might provide some flexibility. There are ...