This map error is caused by the duplicated IO buffers which are located both inside the IP core netlist file (.ngo) and your top-level code that instantiates the IP core netlist. DDR3 IP cores already include all the IO buffers for the DDR3 bus signals inside the ngo file. Therefore, you must disable the IO buffer insertion during the synthesis of your top-level module. You can do this by telling the synthesis tool not to insert any IO buffer to those signals.

The following attribute should be implemented in your Verilog or VHDL top.

  black_box_pad_pin

This tells the synthesis tool that the IO pads are already included in the black box (DDR3 core nelist) so that the top-level does not instantiate the additional IO buffers. See the following examples (The core name is "ddr3core" in this example.):

VHDL:

attribute syn_black_box : string;
attribute syn_black_box of ddr3core : component is true;
attribute black_box_pad_pin : string;
attribute black_box_pad_pin of ddr3core : component is "em_ddr_data(31:0),em_ddr_dqs(3:0),em_ddr_clk(0:0),em_ddr_odt(0:0),em_ddr_cke(0:0),em_ddr_cs_n(0:0),em_ddr_addr(13:0),em_ddr_ba(2:0),em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n" ;

Verilog:

Add the following synthesis directive to the module definition (see a IP core Verilog header file for the complete structure):

/* synthesis syn_black_box black_box_pad_pin="em_ddr_data[63:0],em_ddr_dqs[7:0],em_ddr_clk[0:0],em_ddr_odt[0:0],em_ddr_cke[0:0],em_ddr_cs_n[0:0],em_ddr_addr[27:0],em_ddr_ba[2:0],em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n" */;