5627 - DDR3 3.1 IP Core : Why is the DDR3 IP core is not accessible for ECP3 device when using LSE?

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  Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...

• 2684 - DDR3 IP: Why do I have two top-level wrappers inside a DDR3 IP core package generated from IPexpress ? Which one should I use for my design?

  The DDR3 IP core package includes two top-level wrapper files in two different places using the same name, ddr3_sdram_mem_top_wrapper.v or .vhd. One of them which is located in the directory "ddr_p_eval\<user_name>\impl" is used solely for the core ...

• 1748 - Common Public Radio Interface - IP Core: Do I need to use a clock cleaner when using CPRI IP core (Common Public Radio Interface) with Lattice SERDES based FPGA?

  Lattice CPRI IP core (Common Public Radio Interface) supports LatticeECP2/M, LatticeECP3 and LatticeSC. When using the CPRI IP core in REC(Radio Equipment Control,master) mode, it's not necessary to use a clock cleaner since the system provides the ...

• 2294 - DDR3 PHY:&nbsp; What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?

  Both the data and address/command bus loading factors should be considered to answer the question. The Lattice DDR3 controller and DDR3 PHY IP cores were validated to allow up to two-DDR3 data pin loading on the DQ, DQS and DM signals at the rate of ...

• 7747 - Avant: DDR Memory Controller Revision and Migration Guide

  Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...