PCIe x1
7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?
For ECP3, the recommendations for the SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination. You may refer to the Electrical Recommendations for Lattice ...
7753 - What are the minimum and maximum supported frequencies for aux_clk_i in the FPGA-IPUG-02091: PCIe X1 User Guide?
The recommended operating frequency range for the aux_clk_i signal is as follows: Minimum aux_clk_i frequency: 16 MHz Maximum aux_clk_i frequency: 127 MHz Please ensure that the aux_clk_i signal remains within this range to maintain proper ...
1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?
Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...
3674 - LatticeECP2/ECP3: In Peripheral Component Interconnect Express (PCIe), when an endpoint is in the process of transmitting data to the Root Complex, is the endpoint allowed to send a parallel interrupt?
Description: Yes, when a transaction is in progress from an endpoint of PCIe IP core to the Root Complex, the endpoint can raise a parallel interrupt. However, the interrupt raised by the endpoint is kept in queue and will be processed after ...
3646 - LatticeECP3: Where can I find documentation on the Windows drivers for PCIe Demos that are available for Lattice ECP3 Versa Development Kit?
Description: For details about PCIe drivers for Lattice ECP3 Versa Development Kit, refer to the PCIeDocIndex.html file that is available in the following path of ECP3 Versa Development Kit PCIe installation: DK-ECP3-PCIE-040\Software This file ...
3606 - LatticeECP3: Can we change the DEVSEL parameter to SLOW for the PCIe IP (Peripheral Component Interconnect Express) configuration space?
No, the PCIe (Peripheral Component Interconnect Express) base specification clearly says that the DEVSEL TIMING parameter does not apply to PCIe Express Configuration space and is hardwired 0 by default. This means the DEVSEL TIMING parameter is ...
1104 - LatticeECP3/ECP5: What are Link CRC (LCRC) and End to End Cyclic Redundancy Check (ECRC), and how are they used?
Description:Peripheral Component Interconnect Express (PCIe) provides two different CRC tests for the transfer of data. The LCRC, or Link CRC, is handled in the data link layer. The optional ECRC, or endpoint CRC, is handled in the transaction layer. ...
3601 - LatticeECP3: Why do I need to indicate the Header credits while performing memory reads for the Lattice PCIe IP?
PCIe protocol classifies all transactions in two types: - Posted - Non-posted In posted transactions, the Requester sends the TLP packet to the Completer, and the Completer will not send any completion TLP packet back to the Requester. So, Memory ...
1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?
Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...
1101 - All FPGAs: Why do some PCIe slots run slower than others?
Description: PCIe uses credits to control the flow of TLPs from transmitter to receiver. The amount of credits a port supports directly impacts the throughput of that port. High throughput PCIe slots such as x16 and x8 typically provide 32 or 64 ...
1813 - [PCI Express Endpoint Core]: Why does the Lattice PCI Express X1 Downgrade core that I generated have all channels in the pcs_pipe_8b_xX.txt enabled?
The Lattice PCI Express X1 Downgrade Core is the same as the X4 Native core with the only difference being the value of the MaxLinkWidth field in the LinkCapabilitiesRegister. Although all channels of the SERDES are enabled in the text file as well ...
1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?
The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...
3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?
The Peripheral Component Interconnect Express (PCIe) endpoint IP we have currently can support only up to 8 Message Interconnect Express (MSI) interrupts. This number of MSI interrupts available for the user can be checked in 'Multiple Message ...
3197 - LatticeECP3: Why some interrupts do not reach from PCIe core to CPU, while giving 1 ms interrupt signal to “inta_n” of PCIe core, and then monitoring interrupts at CPU side?
Out of 1000 interrupts, approximately 300 reaches to CPU, when PCIe core’s interrupt assert and de-assert gap is 8 clock duration of wb_clk. When the IP detects that inta_n is asserted low, it needs 8 clocks to create the ASSERT_INTA packet. In case ...
6056 - ECP5/ECP5-5G: What speeds/data rates does the PCIe and PCIe-5G Endpoint IP support?
For ECP5 non-5G devices, PCIe Endpoint IP is to be used. This IP can only support up to Gen1 speed (2.5 Gbps data rate). For ECP5 5G devices, PCIe-5G Endpoint IP is to be used. This IP supports both Gen1 and Gen2 speed (5 Gbps data rate). After ...
7126 - How to disable the PCIe link through PCI Express Capability?
The bit[4] of the Link Control Register can be use to disable the link. Note that this should be directly written from the Root Port and not from the Endpoint (this is a reserved bit for Endpoint). In this example: the setpci command on Linux is use ...
7078 - CertusPro-NX/PCI Express: Why would the host PC crash when running the PCIe DMA Throughput Demo of CertusPro-NX?
Description: The following operation will causes the host PC to crash. - Run Batch Test with Write Operation checked. Solution: Please use the 'Throughput Test' tab instead of the 'Batch Test' tab as it will causes the GUI to crash. Please unselect ...
6215 - Certus Pro-NX: Does Lattice CertusPro-NX supports PCIe via PIPE + Soft PCIELL?
Solution: No, the CertusPro-NX only supports PCIe via PIPE + Hard PCIELL.
4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?
Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...
3997 - [LatticeECP3] [PCIe IP]: Why does the Peripheral Component Interconnect (PCIe) Scatter Gather Direct Memory Access (SGDMA) demo design of LatticeECP3 Versa development kit throw an error when compiled with the standalone Synplify Pro?
Description: When the PCIe SGDMA demo design files are compiled in Synplify Pro, the Synplify Pro compiler considers the variable 'int' to be a System Verilog data type. Solution: This default setting of Synplify Pro is the reason for the error. This ...
7206 - PCIe for Nexus FPGAs: What is the size of the Transmit Buffer and Receive Buffer in PCIe X1 IP Core and PCIe X4 IP Core?
The Transmit Buffer and Receive Buffer size is 2 kByte each. These RAM buffer sizes are fixed because it is a Core internal RAM, so the negotiated Maximum Payload Size (MPS) size will determine how many TLPs can be stored. For instance, in the ...
2069 - LatticeECP3: What is the usage of WB_CTI_I signal in the Lattice PCI Express Scatter Gather DMA Demo design?
WB_CTI_I is a Wishbone user defined signal for tagging the cycle as a single or burst access. In the Lattice PCI Express Scatter Gather DMA Demo design, the signal is driven by the SGDMA IP (Wishbone master). It is sourced by the EBR module (Wishbone ...
7193 - PCIe for Nexus FPGAs: How to generate MSI Interrupts with PCIe x1 IP core?
Solution: To successfully use the MSI Interrupt, the user needs to perform the workaround below. Uncheck the box for "Disable Legacy Interrupt" to enable the Legacy Interrupt. This is a controller code requirement. 'MSI pending bit' = 1 alone does ...
323 - What are the definitions of the BAR bits in PCI/PCIe application?
The bit definitions of BAR for memory base address register are: Bit 0: reserved to 0 as memory space indicator. Bit 2~1: 00 indicates 32-bit access space; while 11 indicates 64-bit access space. Bit 3: 1 indicates that the memory is prefetchable, ...
5787 - During LP mode transmisson, does "hs_en" signal must be tied to High or Low?
Referring to page 3 of RD1182, hs_en (High Speed Enable) is used to reset the alignment module. It depends on the designer on how he/she wanted to set the reset, it can be an active high reset or an active low reset. The following is the descriptions ...
2533 - LatticeECP2M/ECP3: How can I access the full rate recovered clock to sample the receive data in a Lattice X1 Native PCIe IP targeting either LatticeECP2M or LatticeECP3 devices?
Description: The X1 Native PCI Express IP uses the embedded Clock Tolerance Compensation FIFO in the LatticeECP2M/ECP3 SERDES. The receive data coming out of the FIFO is synchronous to the tx_full_clk. This clock should be used if you need to sample ...
1947 - PCIe of LatticeECP3: How should 'tx_req' port should be implemented for better Tx throughput?
For better Tx throughput, tx_req from user logic should be implemented such that gaps in tx_rdy are minimized. The Lattice PCIe IP core arbitrates among user (tx_req) and internal requests to assert tx_rdy to enable packet transmission through the ...
1315 - PCIE IP: Why is a DRC error generated associated with the PCI Core signal/pin serrn (SERR#)?
SERR# is defined as an Open-Drain pin in the PCI Local Bus Specifications. In certain PCI applications, a PCI agent might be required to monitor the SERR# pin so that the agent can properly respond to the system error condition. When using one of the ...
137 - LatticeECP2/M: Why doesn’t the testbench, included in the Basic Demo for the LatticeECP2M PCIe DevKit, simulate properly?
Description: The most likely scenario is the customer using an older version of the software. The LatticeECP2M Basic Demo testbench in the PCIe DevKit requires ispLEVER version 7.2 Service Pack 1 or later. Simulating the testbench with an earlier ...
1301 - PCIe: What Transaction Layer Packets (TLPs) header format is used for 64-bit addressing?
PCIe supports both 32-bit and 64 bit addressing. For 32-bit addressing a 3-DW header is used, containing just 32-bits of address info. For 64-bit addressing, a 4-DW header is used, with the extra DW holding the additional 32-bits of addressing.