7768 - What is the recommended termination when using HCSL input for PCIe Reference Clock?

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• 7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?

  For ECP3, the recommendations for SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination. Refer to the Electrical Recommendations for Lattice SerDes ...

• PCIe DMA in Ring Buffer Operation mode unable to be stopped

  Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...

• 2324 - [LatticeECP3]: Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?

  If the user is using a Lattice DDR3 memory controller IP core version 1.2 or later, the user can use a different rate of input reference clock. The original clock synchronization module (CSM) in the earlier version DDR3 IP cores require the fixed ...

• 130 - When is it appropriate to use dc-coupling with the LatticeECP3 SERDES reference clock?

  The dedicated SERDES reference clock inputs for the LatticeECP3 include default ac-coupling capacitors and optional dc-coupled connections. This dc-coupled connection is available only in the case where an external ac-coupling capacitor is being ...

• 1890 - LatticeECP3: The Lattice SerDeS-based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?

  Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another ...