1813 - [PCI Express Endpoint Core]: Why does the Lattice PCI Express X1 Downgrade core that I generated have all channels in the pcs_pipe_8b_xX.txt enabled?

The Lattice PCI Express X1 Downgrade Core is the same as the X4 Native core with the only difference being the value of the MaxLinkWidth field in the LinkCapabilitiesRegister. Although all channels of the SERDES are enabled in the text file as well as connected in the top level, the setting of MaxLinkWidth (to x1) limits the link and thus traffic to one channel.

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1813 - [PCI Express Endpoint Core]: Why does the Lattice PCI Express X1 Downgrade core that I generated have all channels in the pcs_pipe_8b_xX.txt enabled?

1813 - [PCI Express Endpoint Core]: Why does the Lattice PCI Express X1 Downgrade core that I generated have all channels in the pcs_pipe_8b_xX.txt enabled?

Related Articles

2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

357 - Is is OK to terminate VCCIB/VCCOB (VDDIB/VDDOB) to power on unused SERDES channels of all Lattice SERDES/PCS based devices (LatticeECP2M / LatticeECP3 / LatticeSC/M)?