6215 - Certus Pro-NX: Does Lattice CertusPro-NX supports PCIe via PIPE + Soft PCIELL?

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• 7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?

  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...

• 6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

  CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.

• PCIe: Procedures to run CertusPro-NX PCIe simulation using Cadence Xcelium simulator.

  1. Create a new Radiant project targeting CertusPro-NX. 2. Select IP on Server and install the latest version of PCIE_X4 IP, if it is not yet installed. 3. Switch to IP on Local, double-click PCIE_X4 and enter your desired Component name. 4. ...

• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• 6236 - PCIe for Nexus FPGAs: What is the total amount of PCIe interfaces in CertusPro-NX-100 with different lanes?

  The PCI Express Link Layer Quad for all CertusPro-NX devices has four PIPE interfaces that can be used in different number of links. This can provide the maximum flexibility, depending on the bandwidth of the application requirements. The PCIe link ...