Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...
Description: In PCIe Soft-DMA mode, when an error condition occurs, the DMA IP asserts an interrupt to notify the Host of the detected error. If this interrupt is not properly handled and the DMA is not reset, the system may enter an unrecoverable ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Issue Description/Symptom: The user RTL is unable to write to PCIe Link Layer registers through LMMI when PCIeLL is enabled and accessed on the Hard IP Setup of the Reveal Controller. Figure 1: Root Causes: Reveal will insert a MUX which handles the ...
CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.