PCIe IP Soft-DMA Mode: DMA Reset Required on Error Interrupt Detection

Description:

In PCIe Soft-DMA mode, when an error condition occurs, the DMA IP asserts an interrupt to notify the Host of the detected error. If this interrupt is not properly handled and the DMA is not reset, the system may enter an unrecoverable state, leading to potential data corruption.

Affected Devices:

All devices supporting DMA mode (PCIex1, x4, x8) with AXI Memory Mapped (AXIMM) interface.

Solution:

Upon receiving a DMA error interrupt in Soft-DMA mode, it is recommended that the customer performs a DMA reset to recover gracefully from the error condition. The recommended handling flow is as follows:

1. Host receives DMA error interrupt.

2. Host identifies and logs the specific error type via the DMA status registers.

3. Host issues a DMA reset to clear the error state.

4. Host re-initializes the DMA before resuming operations.

This ensures the DMA IP returns to a known good state and prevents further system instability.

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PCIe IP Soft-DMA Mode: DMA Reset Required on Error Interrupt Detection

PCIe IP Soft-DMA Mode: DMA Reset Required on Error Interrupt Detection

Related Articles

PCIe DMA in Ring Buffer Operation mode unable to be stopped

6978 - PCIe for ECP5: How to disable the Advanced Error Reporting (AER) of the ECP5 PCIe IP ?

6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

3197 - LatticeECP3: Why some interrupts do not reach from PCIe core to CPU, while giving 1 ms interrupt signal to “inta_n” of PCIe core, and then&nbsp;monitoring interrupts at CPU side?&nbsp;

3197 - LatticeECP3: Why some interrupts do not reach from PCIe core to CPU, while giving 1 ms interrupt signal to “inta_n” of PCIe core, and then monitoring interrupts at CPU side?