1947 - PCIe of LatticeECP3: How should 'tx_req' port should be implemented for better Tx throughput?
For better Tx throughput, tx_req from user logic should be
implemented such that gaps in tx_rdy are minimized. The Lattice PCIe IP
core arbitrates among user (tx_req) and internal requests to assert
tx_rdy to enable packet transmission through the user interface. Since
this arbitration can take a few clock cycles, you can implement tx_req
by continuously asserting it high so that arbitration for next packet
occurs during current packet transmission.