5787 - During LP mode transmisson, does "hs_en" signal must be tied to High or Low?
Referring to page 3 of RD1182, hs_en (High Speed Enable) is used to reset the alignment module. It depends on the designer on how he/she wanted to set the reset, it can be an active high reset or an active low reset. The following is the descriptions of ‘hs_en’ signal of RD1182 MIPI D-PHY Rx Interface:
1. Signal ‘hs_en’ is an enable for aligner module, which includes word aligner module (to look for the next HS_Sync sequence/0xB8) and lane aligner module.
2. When ‘hs_en’ is low, the word aligner module is reset. The word aligner module will look for the next HS_Sync sequence again, when ‘hs_en’ changes from low to high.
3. Signal ‘sync’ (output from aligner module) will go high, once the alignment is complete.
4. Signal ‘hs_en’ should remain high unless the user needs to reset the aligner module.
5. Users can set ‘hs_en’ as low to reset aligner module when the output from aligner is incorrect.
NOTE: To set hs_en low to reset the aligner module, keep hs_en low for more than three byte_clk cycles before releasing.
For MIPI D-PHY Rx, signal ‘hs_en’ is only used by aligner module, not directly related to FPGA IO.