5924 - D-PHY to CMOS v1.2/CrossLink: Why does the DPHY RX channel signal did not move from LP to HS mode?

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• 6149 - Crosslink: In dphy_rx_wrap_beh.v, how do user resolve error related to port size mismatch?

  - In dut_inst.v and dut_inst.vhd, the lp_hs_state_d_ port should be lp_hs_state_d_0. - In rx_dphy.v, the following should be inputs: input lp_d0_tx_en_i, input lp_d0_tx_p_i, input lp_d0_tx_n_i.

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  The CrossLink-NX family supports a maximum of 4 virtual channels (VCs) per D-PHY interface when using standard configuration. This limit applies to both hard and soft D-PHY instances, ensuring consistent performance and timing closure across ...

• 5787 - During LP mode transmisson, does "hs_en" signal must be tied to High or Low?

  Referring to page 3 of RD1182, hs_en (High Speed Enable) is used to reset the alignment module. It depends on the designer on how he/she wanted to set the reset, it can be an active high reset or an active low reset. The following is the descriptions ...

• 6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?

  Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...

• 5777 - [CrossLink] [MIPI D-PHY to CMOS Interface Bridge IP]: What can be the cause of frequency calculation error in DPHY to CMOS GPLL after clicking the 'Calculate PLL Frequencies' button of the DPHY-to-CMOS v1.3 Clarity GUI with provided configuration

  With regards to D-PHY to CMOS v1.3 GUI, if the user happens to encounter the dialogue prompt saying that "the desired frequencies for this configuration could not be generated by the PLL", it means that it is not a recommended value that will be used ...