5271 - ECP5/ECP5-5G: What maximum MIPI High Speed (HS) can the Lattice ECP5 IO support?

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• 5787 - During LP mode transmisson, does "hs_en" signal must be tied to High or Low?

  Referring to page 3 of RD1182, hs_en (High Speed Enable) is used to reset the alignment module. It depends on the designer on how he/she wanted to set the reset, it can be an active high reset or an active low reset. The following is the descriptions ...

• 3624 - LatticeECP3: What are the supported rates for Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI) on Lattice ECP3?

  The supported rates for the MIPI CSI RX and TX on Lattice ECP3 -8 speed grade are 550 Mbps and 756 Mbps respectively.

• 1855 - LatticeECP3: What is the recommended cable length for a CAT-6 cable that can be used with SERDES (Serializer/De-Serializer) transmit and receive data at a maximum speed of 3.125Gbps?

  The recommended length of CAT-6 cable that can be supported with a SERDES is 10 feet. For more information, please refer to FPGA-TN-02196 (Transmission of High-Speed Serial Signals over Common Cable Media) for more information.

• 1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

  The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...