137 - LatticeECP2/M: Why doesn’t the testbench, included in the Basic Demo for the LatticeECP2M PCIe DevKit, simulate properly?

• Related Articles

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...

• 6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

  Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.

• 1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?

  Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...

• 3646 - LatticeECP3: Where can I find documentation on the Windows drivers for PCIe Demos that are available for Lattice ECP3 Versa Development Kit?

  Description: For details about PCIe drivers for Lattice ECP3 Versa Development Kit, refer to the PCIeDocIndex.html file that is available in the following path of ECP3 Versa Development Kit PCIe installation: DK-ECP3-PCIE-040\Software This file ...

• 525 - Where is LatticeECP2/M Serdes Reset RTL code ?

  The Reset Sequence code for ECP2/M is included in Serdes demo package. http://www.latticesemi.com/dynamic/view_document.cfm?document_id=24513