7753 - What are the minimum and maximum supported frequencies for aux_clk_i in the FPGA-IPUG-02091: PCIe X1 User Guide?

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• 6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

  Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...

• 7350 - Avant-X 25G Ethernet: Why does Lattice Radiant Software show a critical warning when designing the 25G Ethernet IP on Avant-X FPGA with -2 and -1 performance grades?

  Description: The supported performance grade for Avant-X 25G Ethernet IP is -3 (fastest). Radiant's critical warning as below will appear when using -1 and -2 performance grade devices. This speed grade limitation applies only to Avant-X 25G Ethernet ...

• 6247 - PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?

  Solution: DMA support must be enabled to access the PCIe endpoint through AHB-lite. The DMA (Direct Memory Access) support has an option to enable efficient data transfer when the device acts as an initiator or a master. For more information, refer ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...

• 6220 - CertusPro-NX: How to select the external SerDes reference clock (SD_EXT_x_REFCLKn) of MPCS?

  By using MPCS, the user does not need to specify the location of SD_EXT_x_REFCLKn using a constraint file. Example snippet of the implementation: DIFFCLKIO DIFFCLKIO_inst ( .CLKIN0_P (sd_ext_0_p_i), .CLKIN0_N (sd_ext_0_n_i), .CLKIN1_P (), .CLKIN1_N ...