6247 - PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?

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• 6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?

  clk_usr_o originates from the PCIe Core, bypassing the PCIe Soft IP. It serves as an output to an external pin. Additionally, there are two input clocks for the Soft IP: clk_usr_i at 250 MHz and clk_usr_div2_i at 125 MHz.

• 6927 - PCIe for Nexus FPGAs: Using the Lattice CertusPro-NX PCIe x4 IP Core and the AXI4-Stream interface, what is the latency of read and write access through the APB interface across the Link Layer registers, Configuration Space Registers, and the Soft

  Here is the latency table of the read & write through the APB interface for CertusPro-NX:

• 6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

  Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...

• 6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

  Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.