7350 - Avant-X 25G Ethernet: Why does Lattice Radiant Software show a critical warning when designing the 25G Ethernet IP on Avant-X FPGA with -2 and -1 performance grades?
Description: The supported performance grade for Avant-X 25G Ethernet IP is -3 (fastest).
Radiant's critical warning as below will appear when using -1 and -2 performance grade devices.
This speed grade limitation applies only to Avant-X 25G Ethernet IP. There is no speed grade limitation to 10G Ethernet IP on Avant-G and Avant-X.
Example warning:
CRITICAL <52351082> - Instance '.../lscc_eth25g_ss_top_inst/genblk1.u_lscc_eth25g_phy/secured_instance_29_84/secured_instance_28_0/secured_instance_27_1'(MPPHYX4_MODE) - PROTOCOL=ETHERNET_25G is supported in device LAV-AT-X70 only at -3 performance grade. -2 or -1 performance grade can still run through but will not have any effect.
Solution:
Choose -3 performance grade Avant-X FPGA to implement the 25G Ethernet IP design.
There is no plan for -1 and -2 performance grades to support 25G Ethernet IP.
Related Articles
7747 - Avant: DDR Memory Controller Revision and Migration Guide
Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...
7337 - Avant-G/Avant-X: What is the max peak-to-peak voltage of differential refclk for SERDES?
The max peak-to-peak input voltage of the differential reference clock for Avant-G and Avant-X is 1.15V, with a minimum = -0.3V.
7554 - [Avant-E] SGMII and Gb Ethernet PCS IP Core: Can I implement 2 or 4 SGMII with the Avant-E30?
For Avant SGMII, the Rx data path of each port needs 1 PLL for soft CDR, associated with the HPIO of the same bank. As for Tx, a single PLL can be shared across multiple ports. Therefore, for 2 SGMII, the customer needs 2 + 1 = 3 PLL, and for 4 ...
3524 - Lattice ECP3: How can we access configuration registers of Lattice Tri-Speed Ethernet MAC (TSMAC) IP Core ?
Configuration registers of Tri-Speed Ethernet MAC (TSMAC) IP Core can be accessed through Host Interface. Also, values for particular registers can be hard coded in the ts_mac_core.v file if you are not using any host interface module in your design.
7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...