Synthesis Inquiry / Failure
612 - Lattice Diamond: How can i changed the resource implementation of my Shift register?
Solution 1: The Synthesis tool will determine whether to implement the sequential shift register as register, distribute-RAM or block RAM based on certain criteria. The user can choose a different implementation by specifying "syn_ramstyle" or ...
3175 - Lattice Diamond: What is the maximum allowable project path length in Lattice Diamond to prevent Synthesis Failure?
The maximum project length allowed in Lattice Diamond is same as the maximum allowable path length in Windows operating system which is of 260 characters. Below are the steps to calculate the project path length in diamond. Maximum allowable path ...
1630 - All FPGAs: How can I obtain a Lattice IP Core pre-compiled simulation library that targets my HDL simulation tool of choice?
Description: You do not need to obtain a precompiled simulation library for the Lattice IP Core from Lattice. When you configure and generate the Lattice IP Core in IPexpress, the simulation model for the IP core is generated in an "obfuscated" ...
1623 - All FPGAs: What affect does device family, part density, speed grade, or package selection have on how IPexpress generates a Lattice IP Core?
Description: There is a difference in how the Lattice IP Core is generated between different FPGA families. The difference is not in the functionality, but in the technology elements targeted. For example, the files generated for the IP Core may ...
2997 - Lattice Diamond: How does the synthesis tool treat the unused input and output ports declared in the RTL code and not used(logic is not being assigned to the IO Ports)?
The synthesis tool will remove the unused Input ports declared in the design. For unused Output ports, the tool can either tie them to the GND or leave them tri-stated. You can check this in the RTL view of the Synthesis tool. It is recommended to ...
558 - ABEL Design Language: Can I combine ABEL and HDL source codes in the same project?
In addition to the schematic and ABEL, Verilog, or VHDL project types, Lattice development tools support schematic and Verilog, schematic and VHDL, or EDIF project types. There is no direct way to combine ABEL and HDL source codes into one project. ...
1597 - LatticeXP2: Can I configure LatticeMico32 to run my application after the FPGA is configured, and still have access to LatticeMico32 debug features?
Description: The LatticeMico32 tutorial describes a process for generating a platform intended for use on hardware that has not been fully configured. This initial version is considered a development platform image. The development platform permits ...
549 - Where can I find an explanation of the Syntax and Guidelines for manually editing preference files?
You can find an explanation of the syntax and guidelines for manually editing preference files in the Lattice Diamond online help. Invoke Help->Lattice Diamonnd Help Search for: Preference Syntax In the search results, select "Preference Syntax ...
475 - ispLEVER Classic: How do I setup my favorite synthesis, simulation and editors?
Description: ispLEVER tools come packaged with Synopsys's Synplify Pro synthesis tool (Lattice Device version) and Aldec's Active-HDL (Lattice Edition) simulation environment. These tools only support development for Lattice devices. ispLEVER also ...
1536 - All FPGAs: What is an elf file in LatticeMico8 Mico System Builder (MSB)?
Description: A LatticeMico8 .elf file is a software "Executable Linked Formal" file. The .elf file contains the Mico8 instructions, debug information, and information about the pre-initialized data.The .elf file is included in the directory that the ...
427 - Lattice Diamond: Why does synthesis tool prune counter bits away while they appear to be used in the equations?
Depending on the coding style, signals in the Hardware Description Language (HDL) source code could be removed during the synthesis process. Most of the time it's very obvious why the signals are removed / pruned. But at times it's not clear to the ...
1494 - Lattice ispLever: How to specify where ispLEVER places a register through "synthesis LOC” attribute?
The "synthesis LOC" meta comment should work in Verilog unless there is a syntax error in the code. The correct syntax is the following: reg SamplePhase_90 /* synthesis COMP= SamplePhase_90 LOC="R2C14B" */; A common mistake is to leave out the COMP ...
1492 - Synplify Pro: How do users prevent the Synplify synthesis tool from removing an unused input pin from my design?
Users can prevent Synplify from removing an input pin by setting the syn_force_pads synthesis attribute on the input port. Below a Verilog example: input myinput /* synthesis syn_force_pads=1 */; Below a VHDL example: attribute syn_force_pads: ...
416 - Lattice Diamond: How do I avoid Read Before Write (RBW) memory inference for LatticeECP2/M, LatticeXP2 using Synplify?
Single Port and True Dual Port Memories can be interpreted as Normal and Write Through modes for LatticeECP2/M and LatticeXP2 devices. Another mode that is not supported in these devices is Read Before Write (RBW). Please refer to the device specific ...
2775 - Diamond: How can I add a net that directly connects with an input signal and an output signal in Diamond Schematic Editor ?
In Lattice Diamond Schematic Editor, each input signal and output signal should be connected with an input port and an output port respectively and be named uniquely, and each net has only a single name, therefore, you cannot connect the net with ...
346 - Lattice Diamond: Where can I find a description of Synplify errors and warnings?
In Synplify, select Help->Error Messages An Online Help - Message Viewer window appears. Select the Index tab on the left portion of the window. Select each of the following for more information: error messages, errors, warning messages, and warnings ...
341 - Lattice ispVM system: Can I ignore Synplify Pro "Unrecognized synthesis directive attribute" warnings?
Description: User encounters a warning relating to unrecognized synthesis attributes. This is a known issue on the SW. Solution: The HDL code for blocks that IPexpress generates may contain synthesis properties targeting Exemplar/Precision/Mentor ...
1457 - Synplify Pro: How do I activate the retiming feature in Synplify synthesis flow?
To activate the retiming feature prior to synthesis follow the given steps: Open Synplify tool. Click on the Add Implementation button which can be found on the left-side of the screen Click on the Options tab and check the retiming box.
2633 - How to use PAR_ADJ with FREQUENCY and set the ratio between the clock domains?
PAR_ADJ allows you to loosen requirements for PAR results while tightening up the requirements reported by the timing analysis tool. The variance in required timing values on PAR and TRACE enables you to experiment more efficiently with the strategy ...
5871 - ERROR - <filepath filename="">(line_num): net <net_name> is constantly driven from multiple places at instance <instance_name>, on port <port_name></port_name></instance_name></net_name></filepath>. How to fix it?
The error is caused by modifying a register on two or more different processes, with the first instance found on the line mentioned by the error message (line_num). Sample Code: module sample_multiple_instance(in1, in2, out1); input in1,in2; output ...
7417 - Lattice Diamond: How to create an encrypted netlist?
1) Open the design to encrypt:
232 - ABEL: How to create a schematic symbol for a bus?
The ABEL language does not have a direct way to define a bus for pins. The bus is often defined as such with an internally defined bus. Here is an example: DECLARATIONS CK pin; "Clock input Q8..Q0 pin istype 'reg'; "Counter outputs count = [Q8..Q0]; ...
222 - LatticeSC/M: How should I setup my SPI4.2 IP core power-on reset sequence?
Description: This reset sequence will be for both the LatticeSC/M MACO IP core and the soft IP cores. The recommended power on reset sequence is: Bring up the SPI4.2 transmit (TX) interface of the Network Processing Unit (NPU). The training sequence ...
1249 - Lattice Diamond: Synthesis: How do I initialize ORCALUT via Synthesis?
Lattice Diamond: Synthesis: You can define "init" attribute on a specific ORCALUT4 that you want to instantiate. Synthesis will translate the "init" to appropriate "lut_function" in the edif netlist that it writes out. Below is a small example with ...
162 - Lattice Diamond: How to resolve unexpanded logic block error in Translate Design?
Description: User encounters an error as shown when utilizing IPs with ngo files from Diamond, as shown below: ERROR - logical block 'ddr_top/U1_ddr_sdram_mem_io_top' with type 'ddr_sdram_mem_io_top' is unexpanded. Solution: These errors occur in the ...
2354 - All FPGA: How do I add delay to a net in my design?
Description: To add or control a net's delay manually is useful in some cases to improve hold time or adjust the skew between two nets. In order to add delay to a net, one or more buffers need to be added to the net. You will also need to add ...
2353 - All FPGAs: What is the function of the Synplify Pro's option "Fix Generated Clocks"?
Description: The option is used for the generated-clock conversion. i.e., its values are * 0 – does not convert * 1 – converts; does not report * 2 – converts; reports only sequential elements that could not be converted * 3 (default) – converts; ...
2352 - All FPGAs: Does Lattice Diamond support a parameterized module other than the fixed parameter module generated by IPexpress?
Description: Yes, Lattice Diamond supports a Parameterized Module Instantiation (PMI) flow. PMI modules include PLL, RAM, ROM, FIFO, ADD/SUB, DSP blocks, etc. They can be instantiated easily in Lattice Diamond or ispLEVER. For the details of the ...
7285 - Synplify Pro on Diamond or Radiant: can't see compilation errors
Description: In Diamond or Radiant when using Synplify Pro, there are instances where you are unable to see the error messages on the Message tab. Solution: This is an ongoing enhancement with Synopsys for Radiant and Diamond. This is estimated to be ...
6912 - Diamond: How to avoid optimization of inputs or nets during synthesis?
Description: For keeping the nets during synthesis or in mapping process, the user can use the attribute /* synthesis syn_keep=1 nomerge="on"*/ on the nets or other signal wanted to retain. Refer to this FAQ: ...
6894 - Diamond / Synplify Pro: Why is the Frequency for Synplify Pro Strategy Setting is set to 1 MHz when using the Area preset strategy?
When selecting Area preset strategy, the Frequency setting on the Synplify Pro will change to 1 MHz. If the user changes Frequency setting this to a mid or higher value, the optimization will try to meet that higher frequency and therefore the area ...
7258 - ispLever Classic 2.1 and below: Why does the D Flip-Flop in the post-fit equation of ispLever Classic contain 2 D inputs (D.X1 & D.X2)?
Description: The ABEL engine can extract XOR (exclusive OR) gates wherever possible, it generally gives better Fmax for most designs, so it is the default setting. Compared to the AND-OR logic gate, the XOR logic gate reduces the product term, and ...
7257 - Diamond and Radiant version 2023.2 SP1 and older: HDL Parameter set under Active Implementation options not taking effect in VHDL design when using LSE
Description: In Diamond and Radiant 2023.2 SP1 and older, while using LSE as the Synthesis Tool, the HDL Parameter in Active Implementation options may not take effect. Solution: This is a known issue for VHDL designs. See the following code: ...
7251 - Diamond / Synplify Pro: "WARNING - MT116 |Paths from clock (<clk1_name>:r/f) to clock (<clk2_name>:r/f) are overconstrained because the required time of <delta value="" in="" ns="">ns is too small."</delta></clk2_name></clk1_name>
In Diamond with Synplify Pro as the synthesis tool, these warnings can be observed in the CCK report and the SRR file: CCK Report:
6299 - Diamond: Error: .cckTransfer for write: Permission denied
Description: When trying to synthesize a design using SynplifyPro synthesis tool, below error could occur due to incorrect .cckTransfer file name "Error: .cckTransfer for write: Permission denied" Solution: Rename the .cckTransfer file on the given ...
7245 - Radiant / Synplify Pro: What output file or log file can the user check to further debug issues related to a mixed language design (i.e. VHDL and Verilog source files) when using Synplify Pro as the synthesis tool?
One of the issues users may encounter in a mixed language design is a linking issue between a VHDL component and a Verilog module. For this issue, users can refer to the <impl_name>_comp.linkerlog file on the impl_name --> synwork folder. This would ...
6296 - Lattice Radiant: Why do i encountering an error from duplicate modules when running synthesis?
Description: User is encountering the below error when design is synthesized. ERROR - Duplicate modules named <> between libraries Solution: There are two possible solutions for this error as shown below: (1) Synplify Pro searches for the work.<VHDL ...
7241 - Radiant: How to initialize register values when using LSE synthesis tool?
Description: When initializing the register values using LSE, initializing like below will call the register initialization at post synthesis:
6273 - Diamond 3.12 version SP1 and older: Synthesis fails when Synplify Pro is used on Intel 11th gen and above processors
Description: In Diamond version 3.12 and older, Synthesis may fail when using Synplify Pro if the system uses an Intel 11th Gen and above processor. Solution: The failure occurs when either of the following conditions is met: 1. Encrypted Source is ...
7235 - Lattice Radiant: What does this warning mean "Generated_clock: not connect to any master clock pin."?
Description: The user encounters a WARNING message shown below whenever they utilize a PLL IP. "Generated_clock: not connect to any master clock pin." Solution: The warning implies that the timing engine is indicating that there is no clock at the ...
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