3671 - Diamond: Is there a need to run the complete implementation flow>to view the physical and floor plan views even there is small change in the design?

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• 1805 - Diamond: Can user make post Place and Route (PAR) changes to the design without having to run through the entire Lattice Diamond design flow?

  Changes to the post PAR design are generally refereed to as Engineering Change Orders, or ECOs. The changes are directly written into the Native Circuit Description (.ncd) database file without requiring that user go through the entire design ...

• 7733 - ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

  In Diamond version 3.14, there is a bug where it incorrectly limits the number of PLLs in the device to 0 for LFE5U-12F. Example error message: ERROR - (device oversize error). The number of PLL components needed (1) exceeds the number available. ...

• 5979 - Diamond 3.10: Is there any TCL command for hard-macro (NMC flow) for "Add External Pin" operation?

  Description: External pin declaration is done manually including the declaration of a component to a reference in Diamond. This features should be automated to ensure safety and guarantee that HardMacro will always be added to complete top design, as ...

• 7263 - Lattice Diamond: Are the hold window analysis violations observed on the Timing Analysis View valid timing violations? Do users need to make sure that these are passing even though they are not blocking bitstream generation?

  Even though PAR timing did not show any timing violations, users/designers must check the Timing Analysis View for hold window violations. Hold Window analysis is only for boundary paths, i.e. paths involving input or output ports specified with an ...

• 6142 - Lattice Diamond: Why LSE and Synplify Pro has different RTL View implementation?

  LSE and Synplify Pro use different parsers to parse the design files. LSE uses Verific parser, a third-party tool for Lattice, and the same is used by Netlist Analyzer to infer the RTL view. Synplify Pro uses its own parser, and HDL Analyst uses this ...