ispLever Classic 2.1 and below: Why does the D Flip-Flop in the post-fit equation of ispLever Classic contain 2 D inputs (D.X1 & D.X2)?

ispLever Classic 2.1 and below: Why does the D Flip-Flop in the post-fit equation of ispLever Classic contain 2 D inputs (D.X1 & D.X2)?

Description:
The ABEL engine can extract XOR (exclusive OR) gates wherever possible, it generally gives better Fmax for most designs, so it is the default setting. Compared to the AND-OR logic gate, the XOR logic gate reduces the product term, and then routing complexity/time decreases and Fmax increases.

INTACK1.D = ! INTACK1.D.X1 & INTACK1.D.X2 # INTACK1.D.X1 & ! INTACK1.D.X2

Solution:
You can disable XOR extraction in the following ways:
1. In the right "processes" window, double-click "Optimization Constraint".
2. The "Optimization Constraint Editor" tool is opened.
3. Change the constraint value of "Xor_synthesis" from the default "Yes" to "No", XOR extraction is disabled.
4. Save the changes and close the "Optimization Constraint Editor".
5. Double-click "Fit design" in the right "processes" window.

After that, no more XOR gates are generated in the post-fit equation.