In addition to the schematic and ABEL, Verilog, or VHDL project types, Lattice development tools support schematic and Verilog, schematic and VHDL, or EDIF project types.
There is no direct way to combine ABEL and HDL source codes into one project. If part of the design exists in ABEL while the other part exists in either Verilog or VHDL, users need to generate an internal netlist file for either the ABEL design or the HDL design.
The internal netlist, either the .bl1 file for the CPLD devices, or the .ngo file for the FPGA devices, are generated when the design is fitted, or when the design is successfully synthesized and built. During the generation of the ngo file, it is necessary to turn on the "Disable IO Insertion" during synthesis.
Once generated, the netlist file can be moved into the directory of the final project and be called by the top-level design during the design flow. The netlist file is language-neutral and can be used in either the HDL or ABEL projects.