6912 - Diamond: How to avoid optimization of inputs or nets during synthesis?
Description:
For keeping the nets during synthesis or in mapping process,
the user can use the attribute /* synthesis syn_keep=1 nomerge="on"*/ on the nets or other signal wanted to retain.
Solution:
Verilog example:
input wire A /* synthesis syn_keep=1 NOMERGE="ON" */
VHDL example:
attribute syn_keep : boolean;
attribute syn_keep of A: signal is true;
attribute nomerge : string;
attribute nomerge of A: signal is "ON";