6938 - How to avoid the resource get optimized  during Synthesis?

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• 6912 - Diamond: How to avoid optimization of inputs or nets during synthesis?

  Description: For keeping the nets during synthesis or in mapping process, the user can use the attribute /* synthesis syn_keep=1 nomerge="on"*/ on the nets or other signal wanted to retain. Refer to this FAQ: ...

• 6239 - Synplify Pro: Where to get the detailed information regarding the error code in synthesis?

  Description: After synthesizing the design files while setting the SynplifyPro as synthesis tool, Radiant environment will provide the warnings and errors seen by the synthesis tool, however, detailed information can only be provided inside the ...

• 7769 - Radiant / System Verilog: How to fix the package not found issue for SystemVerilog to avoid synthesis failure?

  Background: 'Package not found' synthesis issue is due to limitation of Radiant to automatically compile RTL files based on its expected arrangement. Solution: Here is the set of instructions to properly compile System Verilog RTL files: 1. In your ...

• 2385 - Modelsim:  After executing the orc_cmpl.bat ModelSim VHDL library compilation script, why do I get errors about unexpanded library elements when I compile my design?

  The following online software documents explain how to compile the VHDL source library files for the stand-alone ModelSim flow: from the Lattice Diamond software tool: select Help-> Lattice Diamond Help. In the new pop-up web browser, select ...

• 200 - Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?

  When user change the PLL phase to improve the Tco, user caan program the PLL phase delay by more than 180 degree, e.g. 315 degree. Its equivalent effect is to advance 45 degree if one clock cycle latency is acceptable. But the Lattice software will ...