222 - LatticeSC/M: How should I setup my SPI4.2 IP core power-on reset sequence?

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• 1237 - Lattice ispLEVER: ispLEVER issued warning for a design with EBR in ASYNC Reset mode

  Lattice ispLEVER: This is due to a hardware restriction and there is a possibility that you may destroy the memory content if this operation isn't performed properly. This is documented in LatticeECP2/M Family Data Sheet (DS1006.pdf, Page 2-20) and ...

• 2781 - Why do I get the message "ERROR - map: IO buffer em_ddr_data_c_0 drives IO buffer em_ddr_data_pad_0 directly, but this is not possible" on most DDR3 interface signals after instantiation of a Lattice DDR3 IP core?

  This FAQ is applicable to all Lattice DDR memory controller IP cores (DDR1/DDR2/DDR3/DDR3-PHY/LPDDR). When a DDR memory interface signal uses a dedicated DDR I/O function, the DDR memory controller or PHY IP core netlist file (.ngo) includes an I/O ...

• 1623 - All FPGAs: What affect does device family, part density, speed grade, or package selection have on how IPexpress generates a Lattice IP Core?

  Description: There is a difference in how the Lattice IP Core is generated between different FPGA families. The difference is not in the functionality, but in the technology elements targeted. For example, the files generated for the IP Core may ...

• 1630 - All FPGAs: How can I obtain a Lattice IP Core pre-compiled simulation library that targets my HDL simulation tool of choice?

  Description: You do not need to obtain a precompiled simulation library for the Lattice IP Core from Lattice. When you configure and generate the Lattice IP Core in IPexpress, the simulation model for the IP core is generated in an "obfuscated" ...

• 1734 - PAC Designer / Power Manager II: How to implement a reset in the code?

  Solution: The reset function can be assigned to an IN Input pin and an equation can be written in the Exceptions or in the Supervisory Logic section. Reset can be accompanied with a Timer and simple or complex equations can be used to activate it. ...