2781 - Why do I get the message "ERROR - map: IO buffer em_ddr_data_c_0 drives IO buffer em_ddr_data_pad_0 directly, but this is not possible" on most DDR3 interface signals after instantiation of a Lattice DDR3 IP core?

2781 - Why do I get the message "ERROR - map: IO buffer em_ddr_data_c_0 drives IO buffer em_ddr_data_pad_0 directly, but this is not possible" on most DDR3 interface signals after instantiation of a Lattice DDR3 IP core?

This FAQ is applicable to all Lattice DDR memory controller IP cores (DDR1/DDR2/DDR3/DDR3-PHY/LPDDR).

When a DDR memory interface signal uses a dedicated DDR I/O function, the DDR memory controller or PHY IP core netlist file (.ngo) includes an I/O buffer that is in conjunction with the required IOLOGIC block. Therefore, you must let the synthesis tool avoid automatic insertion of an additional I/O pad to the signal during the synthesis process. Otherwise, the synthesis tool infers an I/O pad to each of I/O port of your entire design. If the DDR3 interface signal gets the inferred I/O buffer, it will be conflicting with the one inside the netlist file, and this is why you got the error message.

Note that Lattice DDR3 controller/PHY IP core includes the I/O buffers on all DDR3 memory interface signals except the RESET# signal. Other DDR memory IP cores (DDR1/DDR2/LPDDR) include the I/O buffers only on the data (DQ) and data strobe (DQS) signals.

The user design that instantiates the IP core must follow the I/O pad handling configuration shown below:

Verilog:
Use the provided black box core instantiation file ([core_name]_bb.v) found from the core root folder. This black box instantiation file includes the DDR3 signals that should not have additional I/O buffers shown below:

/* synthesis syn_black_box black_box_pad_pin="em_ddr_data[31:0],em_ddr_dqs[3:0],em_ddr_clk[0:0],em_ddr_odt[0:0],em_ddr_cke[0:0],em_ddr_cs_n[0:0],em_ddr_addr[13:0],em_ddr_ba[2:0],em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n" */; //DDR3 32-bit IP core example

/* synthesis syn_black_box black_box_pad_pin="em_ddr_data[31:0],em_ddr_dqs[3:0]" */; //DDR2 32-bit IP core example

VHDL:
Your VHDL design that instantiates the DDR3 core following attribute declaration:

attribute black_box_pad_pin : string;
attribute black_box_pad_pin of ddr3core : component is "em_ddr_data(15:0), em_ddr_dqs(1:0),em_ddr_clk(0:0),em_ddr_odt(0:0),em_ddr_cke(0:0),em_ddr_cs_n(0:0),em_ddr_addr(12:0),em_ddr_ba(2:0),em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n" ; -- DDR3 16-bit example

attribute black_box_pad_pin : string;
attribute black_box_pad_pin of ddr3core : component is "em_ddr_data(31:0),em_ddr_dqs(3:0)"; -- DDR2 32-bit example

The wrapper file (ddr_sdram_mem_top_wrapper.vhd) in the generated core, is a good reference to follow.