The ABEL language does not have a direct way to define a bus for pins. The bus is often defined as such with an internally defined bus.
Here is an example:
DECLARATIONS CK pin; "Clock input
Q8..Q0 pin istype 'reg'; "Counter outputs
count = [Q8..Q0]; "Creating internal bus
EQUATIONS count.clk = CK; "Use internal bus name for logic implementation
count := count + 1;
Problem:
Although the schematic tool allows the user to generate a bus on the symbol from any ABEL module, users often get errors similar to the following:
"Logical Error 13534: Signal 'Q_0_' of Submodule 'count512' can't be used in the interface. Only pin is allowed."
This indicates that lower-level signal names do not match with the top-level names. The top-level schematic signal name Q[0:8] is translated into Q_0, Q_1, etc. They do not match with the Abel pin names Q0, Q1, etc.
Solution:
Users can edit the symbol to link the bus name Q[0:8] to the actual pin names Q0...Q8. Following the steps listed below allows the user to remove the error.
- Open a top-level schematic file that contains the symbol with the bus (count512)
- Click Edit=>symbol
- Click the symbol (count512) in the schematic editor - The Symbol Editor is opened and count512 is shown
- Click Edit=>Attribute=>Pin Name Location - A Dialogue Box "Pin Name" is opened, and "Don't Show" is checked
- Click the pin port Q[0:8] - The Q[0:8] is disable now
- Click Add=>Text, then input "Q[0:8]" and put to the symbol
- Click Edit=>Attribute=>Pin Attribute
- In Pin Attribute Dialogue, click Q[0:8], and change it with Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8
- Save the Symbol Editor and close it
- Save schematic
Now rerun the design flow and the error message should be gone.Related Articles
558 - ABEL Design Language: Can I combine ABEL and HDL source codes in the same project?
In addition to the schematic and ABEL, Verilog, or VHDL project types, Lattice development tools support schematic and Verilog, schematic and VHDL, or EDIF project types. There is no direct way to combine ABEL and HDL source codes into one project. ...
3845 - Diamond: How to create a VHDL output from a schematic file?
You can get a VHDL output from a schematic file by following these steps: 1. In project properties, change the Schematic HDL Type to VHDL. 2. Make any small changes in the schematic file and save it. 3. In the Hierarchy, get the VHDL source code for ...
2228 - PAC Designer: How to change the timer value when using an ABEL design?
When using an ABEL design for the Power Manager II devices, the XLAT_STIMER macro and the XLAT_PRESCALER macro are both only used for simulation. Changing these parameters will NOT affect the setting of the timers in the Power Manager II device ...
2153 - ispLEVER to Diamond: error generated when migrating a schematic-based design?
Description: The normal procedure to migrate a design to Lattice Diamond is by using the “Import ispLEVER Project..” option in the Lattice Design software. While importing, when you check “Copy design source to Implementation’s Source Directory”, all ...
1751 - Schematic Design Entry: How do I add I/O type to a port?
To add an I/O type to a port in the design schematic, users need to first draw (or extend) a wire from the symbol port of their choice. Next, name this wire using the Net Name button. Click the IO Port button and select the type of port (input, ...