Description:

The option is used for the generated-clock conversion. i.e., its values are

* 0 – does not convert
* 1 – converts; does not report
* 2 – converts; reports only sequential elements that could not be converted
* 3 (default) – converts; reports all sequential elements

If a design has an internal clock generated by the logic controlled by an initial clock, Synplify Pro will try to implement the generated-clock logic with the logic that uses the initial clock with an enable when the option is enabled.

With the generated-clock optimization, the original circuit functionality is preserved with the initial clock. One of its advantages is to use the same clock for all logic to simplify the static timing analysis. Another advantage is to save the primary clock resource since fewer clock signals are used. The default setting for the option is 3, i.e., enabled. So the Synplify Pro will perform the optimization by default. But in some cases, the optimization will bring the unwanted side effect of slower design performance.

For example, if the generated clock is the divider output of the initial clock. Its frequency should be lower than the initial clock's. If the generate-clock logic is complex, the frequency of the initial clock may not be easy to meet. You may have to use the MULTICYCLE preference for the logic to relax the performance requirement. If there are no data paths across the generated-clock and the initial clock, or they are treated as asynchronous paths in the design, the optimization can be disabled (i.e., Fix Generated Clocks set to 0). Then the lower frequency constraint will be used for the generated-clock logic to ease the timing requirement.

For more details of this option, please refer to Chapter 7: Specifying Design-Level Optimizations -> Optimizing Generated Clocks in the document "Synopsys FPGA Synthesis Synplify Pro for Lattice User Guide" (user guide).