416 - Lattice Diamond: How do I avoid Read Before Write (RBW) memory inference for LatticeECP2/M, LatticeXP2 using Synplify?

416 - Lattice Diamond: How do I avoid Read Before Write (RBW) memory inference for LatticeECP2/M, LatticeXP2 using Synplify?

Single Port and True Dual Port Memories can be interpreted as Normal and Write Through modes for LatticeECP2/M and LatticeXP2 devices. Another mode that is not supported in these devices is Read Before Write (RBW).
Please refer to the device specific Memory Usage Technical Notes for more details on these modes.
When inferencing the memory, the coding style determines how Synplicity interprets it as - NORMAL, WRITE THROUGH. If the memory is coded in such a way that the last data at the address location that is about to be written into gets pushed out, Synplify may enable the RBW mode for devices like LatticeECP2/M and LatticeXP2. This mode, although supported by Synplicity, is not supported in these devices. If you have a requirement of using this mode, please use LatticeECP3 family, that supports this mode.
The following code of a process declaration in VHDL will generate a memory in RBW mode. In this code the output QA, reads the existing value before write enable WrA goes high. This coding style will be interpretted as a Read Before Write RAM by the synthesis tool. 
test: Process (ClockA, ResetA) begin
if ResetA = '1' then
   QA <= (others => '0');
   elsif ClockA'event and ClockA = '1' then
      if (ClockEnA = '1') then
         if ( WrA = '1' ) then
         Mem(conv_integer (unsigned(AddressA))) <= DataInA;
         end if;
      QA <= Mem(conv_integer (unsigned(AddressA)));
   end if;
end if;
end process;
An RBW RAM will generate a warning in ispLEVER. In order to avoid inferencing of this mode attention should be paid on style. The following coding style is a good example on modifying above code to make sure the supported RAM modes are synthesized. begin
write : process (clk_in)
begin
   if (clk_in'event and clk_in = '1') then
         if (we = '1') then
               mem( conv_integer( addr_in)) <= data_in ;
         end if ;
   end if ;
end process write ;
read : process (clk_out)
begin
   if (clk_out'event and clk_out = '1') then
       data_out <= mem( conv_integer( addr_out)) ;
   end if ;
end process read;
end rtl;This will help making sure the Synplify synthesizes the correct supported modes and avoid warning messages.