1457 - Synplify Pro: How do I activate the retiming feature in Synplify synthesis flow?<br>

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• 7713 - Radiant Synthesis with Synplify Pro: results differ on multiple machines

  Description: When using Synplify Pro on different machines, the system environment could cause different behavior. Some symptoms of this issue include the following: 1. The synthesis behavior is different on another machine (e.g. passes or fails on a ...

• 1048 - Lattice Diamond: Synthesis: Synplify Pro: How to change the type of memory resources Synplify Pro uses when using inferred memory in HDL code?<br>

  Lattice Diamond: Synthesis: Synplify Pro: In many cases HDL code that infers a memory is implemented as EBR-based memory. This can cause issues for a customer who needs to be able to reset this memory to zero during operation. The Synplify compiler ...

• 735 - Lattice Diamond: Synthesis: Synplify Pro: How can I make Synplify Pro infer registers instead of RAM?

  Lattice Diamond: Synthesis: Synplify Pro: There might be situations where you have written Verilog or VHDL code which infers a memory. However the design tools are implementing this as distributed RAM, which can't be initialized or preset to zero. ...

• 7562 - Radiant: The synthesis design process does not complete when synthesis is run on Synplify Pro OEM

  In Radiant, the synthesis and post-synthesis processes are a combined process under "Synthesize Design". When you run synthesis using the standalone version of Synplify Pro, this version generates a .vm file which will be used to run post-synthesis ...

• Synplify Pro: Why is the design failing synthesis when user included Reveal which is previously passing synthesis without Reveal?

  The insertion of Reveal uses Verific's parser instead of Synplify Pro's parser. Due to the difference in parser behavior, there are rare cases that synthesis will pass without Reveal using Synplify Pro's parser, but fail once Reveal is inserted while ...