427 - Lattice Diamond: Why does synthesis tool prune counter bits away while they appear to be used in the equations?
Depending on the coding style, signals in the Hardware Description Language (HDL) source code could be removed during the synthesis process. Most of the time it's very obvious why the signals are removed / pruned. But at times it's not clear to the user why the signals / register bits are optimized away. This often happens when multiple equations have conflicting usage of the signals.
In the example below, the counter bits (CNT) are removed as a result of equation optimization.
- Counter is being used in Dout equation and is ANDed with a decoded address value: Dout <= CNT and (addr = HEX220);
- Then Dout feeds a tri-state equation: D <= Dout when data_bus_oe = '1' else "ZZZZZZZZ";
- The problem occurs when data_bus_oe also depends on the address, but not the same decoded value (addr != HEX220). If (addr= HEX220) is true, then data_bus_oe = 0, thus the Dout is never used when (addr = HEX220) is true. In other words, Dout is always 0 when data_bus_oe = 1. As a result, counter CNT is never used.