7245 - Radiant / Synplify Pro: What output file or log file can the user check to further debug issues related to a mixed language design (i.e. VHDL and Verilog source files) when using Synplify Pro as the synthesis tool?

One of the issues users may encounter in a mixed language design is a linking issue between a VHDL component and a Verilog module. For this issue, users can refer to the <impl_name>_comp.linkerlog file on the impl_name --> synwork folder.

This would show details on why the linking between the Verilog module and the VHDL component failed.

In the example below, the linking failed because of a mismatch in the number of ports between the Verilog module and the VHDL component.