Description:
User is encountering the below error when design is synthesized.
ERROR - Duplicate modules named <> between libraries
Solution:
There are two possible solutions for this error as shown below:
(1) Synplify Pro searches for the work.<VHDL lib> by default causing cyclic dependencies.
The proposed solution is to perform the following:
a. Go to "Project > Active Implementation > Set Top-Level Unit..."
b. Change the library from 'work' to <VHDL lib> (e.g. 'ccr_lat').
c. Click 'OK' then run synthesis.
(2) The cyclic dependencies are also contributed by the top-level filename and its directory.
For this, perform the following:
a. Change the top-level filename that is not similar to the VHDL lib (e.g. from .../ccr_lat/rtl/ccr_lat.vhd to .../ccr_lat/rtl/ccr_lat_top.vhd)
b. Update the top-level on "Project > Active Implementation > Set Top-Level Unit..."
* Note: VHDL Library Name is 'work'*
c. Run synthesis